Founded by Silicon Valley Engineers

India's
Silicon
Education
Stack.

Rayza bridges the gap between Indian academia and global semiconductor industry — through curriculum modernization, faculty upskilling, lab enablement, and industry-led training programs.

Request Institutional Demo → Explore Programs

Curriculum gap

Colleges lag industry by 5–10 yrs

Rayza VLSI Ecosystem

Active Deployment

RTL Design

6 crs

Physical Design

4 crs

Verification

4 crs

Analog / AMS

5 crs

Courses

Semesters

Design Threads

Placement track

FAANG-ready graduates

Our Framework

Four Pillars of
Transformation

Rayza addresses India's semiconductor talent gap from every angle — from freshman curriculum redesign to advanced research labs.

01 / PILLAR

Curriculum Modernization

University syllabi lag industry by 5–10 years. We review, redesign, and realign VLSI coursework with how chips are actually built today — covering RTL, PD, verification, analog, and mixed-signal threads.

SystemVerilogUVM FundamentalsASIC Design FlowOpen-Source EDAAICTE / NEP 2020

02 / PILLAR

Faculty Upskilling

Faculty Development Programs that give professors direct, hands-on exposure to modern RTL, verification, and physical design workflows — taught by engineers who shipped real silicon.

Industry Design FlowsLab DevelopmentProject Mentorship3-Layer Delivery Model

03 / PILLAR

Lab Setup & Enablement

Affordable, scalable semiconductor labs for every engineering college — complete with lab manuals, EDA frameworks, and faculty training. Zero proprietary tool licenses required.

Icarus VerilogVerilatorOpenLaneYosysGTKWave

04 / PILLAR

Industry-Led Student Programs

Practical, project-based training covering RTL design, verification, microarchitecture, physical design, and AI hardware systems — mentored by architects from NVIDIA, Apple, and ARM.

RTL DesignVerificationMicroarchitectureAI HardwarePhysical Design

Flagship Programs

NoC RTL Design
& Microarchitecture

Students graduate with a complete semiconductor design portfolio — from FSM fundamentals to a tape-out-ready 4×4 Mesh Network-on-Chip.

Project-based learning, not passive theory

Mentored by senior industry architects

100% open-source EDA toolchain

Portfolio-ready deliverables each quarter

AICTE compliant credit structure

QUARTER 01

Foundations

SystemVerilog
FSM Design
Valid/Ready Protocols
Skid Buffers
Synchronous FIFOs

QUARTER 02

Advanced Design

Asynchronous FIFOs
CDC Techniques
Round Robin Arbiters
Split/Merge Networks
Credit-Based Flow Control

QUARTER 03

Router Design

5-Port Router
Verification Environment
Throughput Analysis
Deadlock Prevention
XY Routing Logic

QUARTER 04

NoC Capstone

4×4 Mesh NoC
Performance Analysis
Tape-out Portfolio
Industry Review
Placement Readiness

Starting Next Batch · August 2026

CPU RTL Design
& Microarchitecture

A deep-dive into processor microarchitecture — from a clean 5-stage in-order pipeline to a full Tomasulo out-of-order execution engine. Students build and verify a real CPU in RTL, understanding every design decision that modern silicon teams face.

SystemVerilog Pipeline Design OoO Execution Memory Hierarchy Tomasulo Algorithm

5-Stage Pipeline

IF · ID · EX · MEM · WB — hazard detection, forwarding paths, branch prediction, stall logic

Memory Organization

Cache hierarchy design, SRAM arrays, write policies, virtual memory basics, memory-mapped I/O

Tomasulo OoO Architecture

Reservation stations, register renaming, reorder buffer, common data bus, speculative execution

BTech VLSI Program

19-Course, 8-Semester
Curriculum

A Silicon Valley-grade BTech VLSI & Microelectronics curriculum ready for institutional licensing — four design threads, fully AICTE/NBA/NEP 2020 compliant.

Thread 01

RTL & Digital Design

Verilog Fundamentals · SystemVerilog · FSM Design · FIFO Design · NoC Architecture · Advanced RTL

6 Courses

Thread 02

Physical Design

VLSI Fundamentals · Floorplanning · Placement · CTS · Routing · Sign-off Flows

4 Courses

Thread 03

Functional Verification

Verification Methodology · UVM Basics · Constrained Random · Coverage-Driven · Formal Methods

4 Courses

Thread 04

Analog & Circuits

CMOS Circuits · Amplifier Design · LDO Regulators · Switched-Capacitor · gm/ID Methodology · PVT/Monte Carlo

5 Courses

Compliance

Framework Alignment

OBE Framework · AICTE Standards · NBA Accreditation · NEP 2020 · Free Tool Stack Only

Ready to License

Institutional Packages

Structured for
Every College

Three tiers designed around the realities of Indian engineering institutions. Pricing is custom to your institution — reach out and we'll scope a proposal together.

Tier 01

Starter

Starting from ₹8L / year

Ideal for first-time engagement. Curriculum package + one faculty workshop + lab setup guidance.

Curriculum for 2 core VLSI courses
1 Faculty Development Workshop (3 days)
Open-source lab setup manual
Student study materials
Email support + quarterly review

Request Proposal

Feedback from
Students & Faculty

Early reviews from engineers who've gone through Rayza's NoC RTL Design program.

Thank you for helping me with my interview preparation. The mock interviews helped me understand the areas where I needed to improve and made me much more confident in my interviews.

Rahul Powar

Interview Prep · Mentee

Anuj doesn't simply recount his career milestones—he shares the deeper "how" behind each transition. With incredible clarity, he describes the decisions, challenges, and opportunities that shaped his path across Intel, Apple, and NVIDIA. What truly sets Anuj apart is his kindness and precision. When he offers advice, it's not vague or generic—he gives practical, exact solutions. He guided not just with expertise, but with a genuine desire to see others succeed. His thoughtful guidance has shaped my own journey for the better. Anuj doesn't just guide you—he empowers you to reach success in the most thoughtful, authentic way.

Abinands

Career Mentee

Learning from Anuj has been an exceptional experience. His journey through NVIDIA, Apple, and Intel has given him a rare blend of technical mastery and industry perspective that he shares with remarkable clarity. Every conversation with him leaves you thinking differently — more critically, more creatively. What stands out most is his willingness to go beyond the expected. Anuj doesn't just share knowledge; he builds confidence and curiosity. I'm genuinely thankful for the time and insight he's invested in my growth.

Anonymous

via Topmate

Topmate

The Engineer Behind Rayza

NVIDIA · Senior HW Design Engineer

MS Electrical Engineering · USC

Founder & CEO

Anuj Panwar

Senior Hardware Design Engineer · NVIDIA

Anuj Panwar is a Senior Hardware Design Engineer with over a decade of silicon experience spanning NVIDIA, Apple, Intel, and ARM — covering RTL design, microarchitecture, custom circuits, physical design, and SRAM development.

He built Rayza out of a conviction that Indian engineering students deserve Silicon Valley-grade education infrastructure — not just a course, but a complete ecosystem upgrade that transforms how semiconductor engineering is taught.

Expertise

RTL · Microarchitecture · Circuits

Domain

Physical Design · SRAM · Display IP

Industry

10+ Years Silicon Pedigree

Vision

Sovereign Indian Silicon

Get in Touch

Ready to Transform
Your Institute?

Full Name

Role

Institution

Message

Book a 15-min Call

with Anuj Panwar · Founder

Talk directly with Anuj about curriculum transformation, faculty upskilling, or the student program. No sales pitch — just a focused conversation about your institution's needs.

Curriculum scoping Faculty programs Student batches

Schedule on Topmate

anujpanwar@rayza.in

Website

rayza.in

Who We Work With

Professors · Department Heads · Deans · VCs · Government Officials

Presence

Pan India

India'sSiliconEducationStack.

Four Pillars ofTransformation

Curriculum Modernization

Faculty Upskilling

Lab Setup & Enablement

Industry-Led Student Programs

NoC RTL Design& Microarchitecture

CPU RTL Design& Microarchitecture

19-Course, 8-SemesterCurriculum

Structured forEvery College

Feedback fromStudents & Faculty